NetSilicon® NET+40

El NET+40 de NetSilicon es un microprocesador de alto rendimiento de 32 bits altamente integrado, diseñado para utilizarlo en dispositivos inteligentes conectados a la red y aparatos de Internet. Lleva un procesador central ARM7TDMI, MAC de Ethernet 10/100BaseT integral con una interfaz MII, controlador DMA patentado de 10 canales y un sofisticado controlador de memoria compatible con todos los dispositivos de memoria más utilizados hoy en día.

El NET+40 forma parte de la galardonada familia NET+ARM de microprocesadores de red. Esta familia brinda facilidad de ampliación y compatibilidad de pines en diversas categorías de rendimiento. Los microprocesadores NET+ARM son los módulos centrales de la plataforma NET+Works® de soluciones altamente integradas y probadas para dotar de inteligencia y conectividad a dispositivos electrónicos.

• 32-Bit ARM7TDMI RISC
• On-Chip Cache
• Integral 10/100 Ethernet MAC
• 10-Channel DMA Controller
• Serial Ports
• Bus Interface
• Timers
• General Purpose I/O
• Clock Generator
• Package
• Other

32-Bit ARM7TDMI RISC Processor

• Full 32-bit ARM mode
• 15 general-purpose 32-bit registers
• 32-bit program counter and status register
• 5 supervisor modes, 1 user mode

On-Chip Cache

• 4K unified instruction/data cache
• 4-way set associative
• Lockable entries
• Write through/copy back

Integral 10/100 Ethernet MAC

• 10/100Mbit MII based PHY interface
• 10Mbit ENDEC interface
• Supports TP-PMD and fiber-PMD devices
• Full duplex
• Optional 4B/5B scrambling
• Full statistics gathering (SNMP and RMON)
• Station, broadcast, multicast address detection and filtering
• 128 byte transmit FIFO
• 2K byte receive FIFO
• Intelligent receive side buffer selection
• External CAM filtering

10-Channel DMA Controller

• 2 dedicated to Ethernet transmit/receive
• 4 dedicated to serial transmit/receive
• 2 dedicated to P1284 interface
• Flexible buffer management
• 2 channels configurable for external peripherals

Serial Ports

• 2 fully independent HDLC/UART/SPI serial ports
• 32 byte transmit/receive FIFOs
• Internal programmable bit-rate generators
• Bit rates from 75 bps – 230.4 kbps: 16X mode
• Bit rates from 1200 – 4Mbps: 1X mode
• Odd, even, or no parity
• 5, 6, 7 or 8 bits
• 1 or 2 stop bits
• Both internal and external clock support
• Receive side character and buffer gap timers
• 4 receive side data match detectors

Bus Interface

• 5 independent programmable chip selects
• Supports 8-, 16-, 32-bit peripherals
• Supports external address decoding and cycle termination
• Supports dynamic bus sizing
• Supports ASYNC and SYNC peripheral timing
• All chip selects support SRAM, EDO DRAM, SDRAM, Flash, EEPROM without external glue logic
• Internal DRAM address multiplexing
• Internal refresh controller (CAS before RAS)
• 256Mbyte addressing per chip select
• Burst-mode support
• 0-15 wait states per chip select
• Bootstrap support
• External bus master support
• Internal or external bus arbiters P1284/ENI Interface
• 4 IEEE 1284 parallel ports
• 64 kB shared RAM ENI interface (8 or 16-bit)
• Full duplex FIFO mode interface (8 or 16-bit)
• 32 byte transmit/receive FIFOs

Timers

• Two independent 26-bit programmable timers
• Programmable watch-dog timer (interrupt or reset on expiration)
• Programmable bus timer

General Purpose I/O

• Up to 24 programmable I/O pins
• 4 pins with programmable interrupt

Clock Generator

• Simple external crystal
• On-board programmable phase lock loop
• Supports direct external clock input

Package

• 208-pin PQFP, 0.020 inch (0.5 mm) pitch

Other

• Operating voltage – 3.0 – 3.6V
• Industrial temperature range (-40º C to 85º C)