NetSilicon® NET+50

El NET+50 de NetSilicon es un microprocesador económico de alto rendimiento de 32 bits conectado a la red pensado especialmente para aplicaciones que precisen gran ancho de banda en dispositivos inteligentes conectados a la red. El NET+50 forma parte de la galardonada familia NET+ARM de soluciones de "sistema en un chip" para sistemas integrados. Basado en la arquitectura de ARM, integra MAC de Ethernet 10/100Base-T con una interfaz MII, un controlador DMA distribuido de 10 canales y un controlador de memoria compatible con todos los dispositivos de memoria más utilizados hoy en día.

Combinado con el software de conexión a redes NET+Works® y las herramientas de desarrollo integradas, el NET+50 brinda el método mejor y más rápido de conectar su dispositivo a una red.

El NET+50 cumple la normativa relativa a la restricción del uso de materiales peligrosos (RoHS).

• 32-Bit ARM7TDMI RISC
• On-Chip Cache
• Integral 10/100 Ethernet MAC
• 10-Channel DMA Controller
• Serial Ports
• Bus Interface
• Timers
• General Purpose I/O
• Clock Generator
• Package
• Other
• Details on ARM7 Core

32-Bit ARM7TDMI RISC Processor

• Full 32-bit ARM mode
• 15 general-purpose 32-bit registers
• 32-bit program counter and status register
• 5 supervisor modes, 1 user mode
• 44 MHz bus speed

On-Chip Cache

• 8 KB internal cache or 16 KB RAM
• 4-way set associative
• Lockable entries
• Write through

Integral 10/100 Ethernet MAC

• 10/100Mbit MII based PHY interface
• Supports TP-PMD and fiber-PMD devices
• Full- or half duplex
• Optional 4B/5B scrambling
• Full statistics gathering (SNMP and RMON)
• Station, broadcast, multicast address detection and filtering
• 128 byte transmit buffer
• 2K byte receive buffer
• Intelligent receive side buffer selection
• External CAM filtering

10-Channel DMA Controller

• 2 dedicated to Ethernet transmit/receive
• 4 dedicated to serial transmit/receive
• 2 dedicated to P1284 interface
• Flexible buffer management
• 2 channels configurable for external peripherals

Serial Ports

• 2 fully independent HDLC/UART/SPI serial ports
• 32 byte transmit/receive FIFOs
• Internal programmable bit-rate generators
• Bit rates from 75 bps – 230.4 kbps: 16X mode
• Bit rates from 1200 – 4Mbps: 1X mode
• Odd, even, or no parity
• 5, 6, 7 or 8 bits
• 1 or 2 stop bits
• Both internal and external clock support
• Receive side character and buffer gap timers
• 4 receive side data match detectors

Bus Interface

• 5 independent programmable chip selects
• Supports 8-, 16-, 32-bit peripherals
• Supports external address decoding and cycle termination
• Supports dynamic bus sizing
• Supports ASYNC and SYNC peripheral timing
• All chip selects support SRAM, EDO DRAM, SDRAM, Flash, EEPROM without external glue logic
• Internal DRAM address multiplexing
• Internal refresh controller (CAS before RAS)
• 256Mbyte addressing per chip select
• Burst-mode support
• 0-15 wait states per chip select
• Bootstrap support
• External bus master support
• ENI/GPIO interface using shared pins
• 4 IEEE 1284 parallel ports
• 64 kB shared RAM ENI interface (8 or 16-bit)
• Full duplex FIFO mode interface (8 or 16-bit)
• 32 byte transmit/receive FIFOs

Timers

• 2 independent 27-bit programmable timers
• Programmable watch-dog timer (interrupt or reset on expiration)
• Programmable bus timer

General Purpose I/O

• Up to 40 programmable I/O pins
• Up to 32 general purpose input pins
• 36 pins with programmable interrupt

Clock Generator

• Simple external crystal
• On-board Phase Locked Loop
• Supports direct external clock input

Package

• 208-pin BGA, 0.8mm pitch
• PQFP

Other

• Operating voltage:
  • Core: 2.5V ± 10%
  • I/O Ring: 3.3V ± 10%
• Operating temperature range: -40º C to 85º C
• Supported by NET+Works development software

Details on ARM7 Core

• 32/16-bit RISC architecture (ARM v4T)
• 32-bit ARM instruction set for maximum performance and flexibility
• 16-bit Thumb instruction set for increased code density
• Unified bus interface, 32-bit data bus carries both instructions and data
• Three-stage pipeline 32-bit ALU
• Very small die size and low power consumption
• Fully static operation
• Coprocessor interface
• Extensive debug facilities:
  • EmbeddedICE-RT real-time debug unit
  • JTAG interface unit
  • Interface for direct connection to Embedded Trace Macrocell (ETM)