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NS9360


32-bit ARM926EJ-S RISC Processor

  • 103, 155, 177 MHz
  • 5-stage pipeline
  • Harvard architecture
  • 8 kB I-Cache and 4 kB D-Cache
  • 32-bit ARM and 16-bit Thumb instruction sets, can be mixed for performance/code density tradeoffs
  • MMU to support virtual memory based OS’s such as Linux, WinCE/Pocket PC, VxWorks, others
  • DSP instruction extensions, improved divide, single cycle MAC
  • ARM Jazelle, 1200CM (CoffeeMarks) Java Accelerator
  • Embedded ICE-RT debug unit
  • JTAG boundary scan, BSDL support
  • Clock-gated processor for decreased power dissipation

External System-Bus Interface

  • 32-bit data bus, 32-bit internal address bus, 28-bit external address bus
  • Glueless interface to SDRAM,SRAM, EEPROM, buffered DIMM, Flash
  • Up to 256 MB SDRAM, up to 2 GB DIMM
  • 4 static and 4 dynamic memory chip selects
  • 0-63 wait states per chip select
  • Self-refresh during system sleep mode
  • Automatic dynamic bus sizing to 8-bits, 16-bits, 32-bits
  • Burst-mode support with automatic data width adjustment
  • 2 external DMA channels for external peripheral support

System Boot

  • High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash
  • Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending)

High-Performance 10/100 Ethernet MAC

  • MII/RMII PHY interfaces
  • Full-duplex or half-duplex
  • Station, broadcast, or multicast address filtering
  • 2 kB RX FIFO
  • 256B Tx FIFO with on-chip buffer descriptor ring (Eliminates under runs and decreases bus traffic)
  • Separate Tx and Rx DMA channels
  • Intelligent receive-side buffer size selection
  • Support for full statistics gathering
  • Support for external CAM filtering

Flexible LCD Controller

  • Supports commercially available displays up to SVGA
  • Active Matrix color TFT displays
  • Up to 18 bpp; 256k colors
  • Single- and dual-panel color
    • Up to 16 bpp 4:4:4 RGB; 3375 colors
  • Single and dual-panel monochrome STN displays
  • 1, 2, 4 bpp palletized grayscale
  • Formats image data and generates timing control signals
  • Internal programmable palette-LUT and grayscaler support different color techniques
  • Programmable panel-clock frequency

USB Ports

  • USB v.2.0 Full speed (12 Mbps) and Low speed (1.5 Mbps)
  • OHCI host and 13 end point device
  • Single PHY can be used with either host or device
  • Interface to external PHY for simultaneous host and device operation
  • Each USB device endpoint is supported by a dedicated DMA channel, 13 total
  • 20B Rx FIFO and 20B Tx FIFO

Serial Ports

  • 4 serial modules, each independently configurable to UART mode, HDLC mode, SPI Master mode, or SPI Slave mode
  • Bit rates from 75 bps to 1.8 Mbps:asynchronous x8 mode
  • Max bit rates for synchronousmode are:
    • 1/16 CPU speed for SPI master
    • 1/32 CPU speed for SPI slave
  • UART provides
    • High-performance hardware and software flow control
    • Odd, even, or no parity- 5, 6, 7 or 8 bits
    • 1 or 2 stop bits
    • Receive-side character and buffer gap timers
  • Internal or external clock support, digital PLL for Rx clock extraction
  • 4 receive-side data match detectors
  • 2 dedicated DMA channels per module, 8 channels total
  • 32 byte Tx FIFO and 32 byte RxFIFO per module

I2C Port

  • I2C v.1.0, configurable to Master or Slave mode
  • Bit rates: fast (400 kHz) or normal (100 kHz) with clock stretching
  • 7-bit and 10-bit address modes

1284 Parallel Peripheral-to-Host Port

  • All standard modes:
    • ECP, Byte, Nibble, Compatibility
  • RLE (Run Length Encoding) decoding of compressed data in ECP mode
  • Operating clock from 100 kHz to 2 MHz
  • 4 dedicated DMA channels
    • 2 for data and 2 for control
  • Microsoft Plug-and-Play, no Windows driver needed

System Bus DMA

  • Every system bus peripheral is a bus master with dedicated DMA engine
  • Deterministic bus bandwidth allocation (patent pending)

Peripheral Bus DMA

  • 13-channel engine supports USB Device
    • 2 DMA channels support control endpoint
    • 11 DMA channels support 11 endpoints
  • 12-channel engine supports
    • 4 serial modules (8 DMA channels)
    • 1284 parallel port (4 DMA channels)
  • All DMA channels support fly-by mode

External Peripheral DMA

  • One 2-channel DMA engine supports external peripheral connected to memory bus
  • Each DMA channel supports memory-to-memory transfers

Power Management (Patent Pending)

  • Power save during normal operation
    • Disables unused modules
  • Power save during sleep mode
    • Sets memory controller to refresh
    • Disables all modules except selected wakeup modules
    • Wakeup on valid packets or characters
  • Patent pending technology

Vector Interrupt Controller

  • Holds pointers to all interrupt service routines for rapid service
  • Services all peripherals
  • Hardware interrupt prioritization

General Purpose Timers/Counters/PWN

  • 8 independent 16- or 32-bit programmable timers, counters, or 4PWM functions
  • Each has an I/O pin
  • Mode selectable into:
    • Internal timer mode
    • External gated timer mode
    • External event counter
    • PWM
  • Timers/counters can be concatenated
  • Minute-range events measurable
  • Source clock selectable
  • Internal clock or external pulse event
  • Individually enabled/disabled

System Timers

  • Watchdog timer
  • System bus monitor timer
  • Peripheral bus monitor timer

General Purpose I/O

  • 73 programmable GPIO pins (muxed with other functions)
    • includes 7 high-current (8mA) GPIO pins
  • Software-readable power-up status registers for customer-defined bootstrapping

External Interrupts

  • 4 external programmable interrupts
    • Rising or falling edge-sensitive
    • Low level- or high level-sensitive

Real Time Clock

  • Time of day clock
  • Alarm
  • 100 year calendar
  • Programmable periodic interrupt
  • 10 ms resolution
  • Dedicated time domain in the system PLL
    • RTC-only mode available
  • Initial time from network through SNTP routine
  • No battery backup
  • Additional benefits
    • Frees CPU from math calculations
    • Decreased response time for queries

Clock Generator

  • Low-cost external crystal
  • On-chip phase locked loop (PLL)
  • Software programmable PLL parameters
  • Optional external oscillator
  • Separate PLL for USB

Operating Voltage

  • Core: 1.5V ± 0.1V
  • I/O Ring: 3.3V ± 10%

Operating Frequency

  • 103 MHz: 0 °C to 70 °C
  • 155 MHz: -40 °C to +85 °C
  • 177 MHz: 0 °C to 70 °C

Power Consumption

  • 177 MHz: 1.35W max (estimated)

Package

  • 272-pin BGA including 16 thermal balls
  • 1.27 mm ball pitch
  • 27 mm x 27 mm
  • Lead-free; RoHS compliant

Details on ARM9 Core

  • 32/16-bit Harvard RISC architecture with 5 stage pipeline (ARMv5TEJ)
  • 32-bit ARM instruction set for maximum performance and flexibility
  • 16-bit Thumb instruction set for increased up to 35% code density
  • DSP instruction extensions and single cycle MAC
  • ARM Jazelle technology, 6 CM/MHz = 1200 Caffeine Marks @ 200 MHz
  • MMU which supports Windows CE and Linux
  • EmbeddedICE-RT logic for real-time debug

 

 

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