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NS9775


32-bit ARM926EJ-S RISC Processor

  • 200 MHz
  • 5-stage pipeline
  • Harvard architecture
  • 8 kB I-Cache and 4 kB D-Cache
  • 32-bit ARM and 16-bit Thumb instruction sets, can be mixed for performance/code density tradeoffs
  • MMU to support virtual memory based OS’s such as Linux, WinCE/Pocket PC, VxWorks, others
  • DSP instruction extensions, improved divide, single cycle MAC
  • ARM Jazelle, 1200CM (CoffeeMarks) Java Accelerator
  • Embedded ICE-RT debug unit
  • JTAG boundary scan, BSDL support

Print Engine Controller

  • 4 parallel JBIG decoders
    • Internal bypass foruncompressed data
    • Automatic and manual headerprocessing modes
  • Glueless interface to most printengines
    • 4 data ports for color tandemprinters
    • Single port for 4-pass colorprinters
    • Single port for monochromeprinters
  • Up to 13” lines at 2400 dpi Up to 13” lines at 2400 dpi Up to 13” lines at 2400 dpi Up to 13” lines at 2400 dpi
  • High print speed:
    • Tandem: 90 ppm
    • 4-pass color: 22 ppm
    • Monochrome: 90 ppm
  • These conditions yield the above performance:
    • Page size: 8.5” x 11”
    • Resolution: 600 x 600 dpi
    • Video clock: 100 MHz
    • Horizontal correction factor: 0.7
    • Vertical correction factor: 0.7
  • Asynchronous print mode with internal PLL
    • Clock rates up to 100 MHz
  • Synchronous print mode with 1or 4 external clocks:
    • Clock rates up to 200 MHz
  • Bus Master on the system bus and a dedicated 4-channel DMA engine, one per color plane
  • On-chip input and output FIFOs,one pair per color plane
  • General communication through serial and GPIO ports

External System-Bus Interface

  • 32-bit data bus, 32-bit internal address bus, 28-bit external address bus
  • Glueless interface to SDRAM,SRAM, EEPROM, buffered DIMM, Flash
  • 4 static and 4 dynamic memory chip selects
  • 0-63 wait states per chip select
  • Self-refresh during system sleep mode
  • Automatic dynamic bus sizing to 8-bits, 16-bits, 32-bits
  • Burst-mode support with automatic data width adjustment
  • 2 external DMA channels for external peripheral support

System Boot

  • High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash
  • Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending)

High-Performance 10/100 Ethernet MAC

  • 10/100 Mbps MII/RMII PHY interfaces
  • Full-duplex or half-duplex
  • Station, broadcast, or multicast address filtering
  • 2 kB RX FIFO
  • 256 byte Tx FIFO with on-chip buffer descriptor ring
    • Eliminates under runs and decreases bus traffic
  • Separate Tx and Rx DMA channels
  • Intelligent receive-side buffer size selection
  • Full statistics gathering support
  • External CAM filtering support

PCI/CardBus Port

  • PCI v.2.2, 32-bit bus, up to 33 MHz bus speed
  • Programmable to:
    • PCI device mode
    • PCI host mode: Supports up to 3 external PCI devices (embedded PCI arbiter or externalarbiter)
    • CardBus host mode

Flexible LCD Controller

  • Supports most commercially available displays
    • Active Matrix color TFT displays: Up to 24bpp direct 8:8:8 RGB;16M colors
    • Single- and dual-panel color
    • STN displays:Up to 16bpp 4:4:4 RGB;3375 colors
    • Single- and dual-panelmonochrome
    • STN displays:1, 2, 4bpp palettized gray scale
  • Formats image data and generates timing control signals
  • Internal programmable palette-LUT and grayscaler support different color techniques
  • Programmable panel-clock frequency

USB Ports

  • USB v.2.0 Full speed (12 Mbps) and Low speed (1.5 Mbps)
  • Configurable to device or OHCI host
    • USB host is a bus master
    • USB device supports one bi-directional control endpoint and 11 unidirectional endpoints
  • All endpoints supported by a dedicated DMA channel; 13 channels total
  • 20B Rx FIFO and 20B Tx FIFO

Serial Ports

  • 4 serial modules, each independently configurable to UART mode, HDLC mode, SPI Master mode, or SPI Slave mode
  • Bit rates from 75 bps to 921.6 kbps: asynchronous x16 mode
  • Bit rates from 1.2 kbps to 6.25 Mbps: synchronous mode
  • UART provides
    • High-performance hardware and software flow control
    • Odd, even, or no parity
    • 5, 6, 7 or 8 bits
    • 1 or 2 stop bits
    • Receive-side character and buffer gap timers
  • Internal or external clock support, digital PLL for Rx clock extraction
  • 4 receive-side data match detectors
  • 2 dedicated DMA channels per module, 8 channels total
  • 32 byte Tx FIFO and 32 byte RxFIFO per module

I2C Port

  • I2C v.1.0, configurable to Master or Slave mode
  • Bit rates: fast (400 kHz) or normal (100 kHz) with clock stretching
  • 7-bit and 10-bit address modes
  • Supports I2C bus arbitration

1284 Parallel Peripheral Port

  • All standard modes:
    • ECP, Byte, Nibble, Compatibility (also known as SPP or“Centronix”)
  • RLE (Run Length Encoding) decoding of compressed data in ECP mode
  • Operating clock from 100 kHz to 2 MHz

High Performance Multiple-Master/Distributed DMA System

  • Intelligent bus bandwidth allocation (patent pending)
  • System bus and peripheral bus

System Bus

  • Every system bus peripheral is a bus master with a dedicated DMA engine

Peripheral Bus DMA

  • One 13-channel engine supports USB device
    • 2 DMA channels support control endpoint
    • 11 DMA channels support 11 endpoints
  • One 12-channel engine supports
    • 4 serial modules (8 DMA channels)
    • 1284 parallel ports (4 DMA channels)
  • All DMA channels support fly-by mode

External Peripheral DMA

  • One 2-channel DMA engine supports external peripheral connected to memory bus
  • Each DMA channel supports memory-to-memory transfers

Power Management (Patent Pending)

  • Power save during normal operation
    • Disables unused modules
  • Power save during sleep mode
    • Sets memory controller to refresh
    • Disables all modules except selected wakeup modules
    • Wakeup on valid packets or characters

Vector Interrupt Controller

  • Decreased bus traffic and rapid interrupt service
  • Hardware interrupt prioritization

General Purpose Timers/Counters

  • 16 independent 16-bit or 32-bit programmable timers or counters
    • Each has an I/O pin
  • Mode selectable into:
    • Internal timer mode
    • External gated timer mode
    • External event counter
  • Can be concatenated
  • Resolution to measure minute-range events
  • Source clock selectable: internal clock or external pulse event
  • Each can be individually enabled/disabled

System Timers

  • Watchdog timer
  • System bus monitor timer
  • System bus arbiter timer
  • Peripheral bus monitor timer

General Purpose I/O

  • 50 programmable GPIO pins (muxed with other functions)
  • Software-readable power-up status registers for every pin for customer-defined bootstrapping

External Interrupts

  • 4 external programmable interrupts
    • Rising or falling edge-sensitive
    • Low level- or high level-sensitive

Clock Generator

  • Low-cost external crystal
  • On-chip phase locked loop (PLL)
  • Software programmable PLL parameters
  • Optional external oscillator
  • Separate PLL for USB

Operating Grades/Ambient Temperatures

  • 200 MHz: 0° C to 70° C

Details on ARM9 Core

  • 32/16-bit Harvard RISC architecture with 5 stage pipeline (ARMv5TEJ)
  • 32-bit ARM instruction set for maximum performance and flexibility
  • 16-bit Thumb instruction set for increased up to 35% code density
  • DSP instruction extensions and single cycle MAC
  • ARM Jazelle technology, 6 CM/MHz = 1200 Caffeine Marks @ 200 MHz
  • MMU which supports Windows CE and Linux
  • EmbeddedICE-RT logic for real-time debug

 

 

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