NS9750

• 32-bit system-on-chip with ARM926EJ-S core
• Up to 200 MHz with 8/4 KB of I-/D-cache
• On-chip 10/100 Mbit Ethernet MAC
• Integrated 32-bit PCI v2.2 with Cardbus support
• Industrial and commercial operating temperature
• Product brief

The NS9750 is a member of the Digi NET+ARM family of 32-bit processors. It is a highly integrated network-enabled processor with a 200 MHz ARM926EJ-S core for use in intelligent networked devices and Internet appliances, where performance, price and a rich set of peripherals are needed.

• 32-bit ARM926EJ-S RISC Processor
• External System-Bus Interface
• System Boot
• High-Performance 10/100 Ethernet MAC
• PCI/CardBus Port
• Flexible LCD Controller
• USB Ports
• Serial Ports
• I²C Port
• 1284 Parallel Peripheral Port
• High Performance Multiple-Master/Distributed DMA System
• System Bus
• Peripheral Bus DMA
• External Peripheral DMA
• Power Management (Patent Pending)
• Vector Interrupt Controller
• General Purpose Timers/Counters
• System Timers
• General Purpose I/O
• External Interrupts
• Clock Generator
• Operating Voltage
• Operating Frequency
• Power Consumption
• Package
• Details on ARM9 Core

32-bit ARM926EJ-S RISC Processor

• 200 MHz
• 5-stage pipeline
• Harvard architecture
• 8 kB I-Cache and 4 kB D-Cache
• 32-bit ARM and 16-bit Thumb instruction sets, can be mixed for performance/code density tradeoffs
• MMU to support virtual memory based OS’s such as Linux, WinCE/Pocket PC, VxWorks, others
• DSP instruction extensions, improved divide, single cycle MAC
• ARM Jazelle, 1200CM (CoffeeMarks) Java Accelerator
• Embedded ICE-RT debug unit
• JTAG boundary scan, BSDL support

External System-Bus Interface

• 32-bit data bus, 32-bit internal address bus, 28-bit external address bus
• Glueless interface to SDRAM,SRAM, EEPROM, buffered DIMM, Flash
• 4 static and 4 dynamic memory chip selects
• 0-63 wait states per chip select
• Self-refresh during system sleep mode
• Automatic dynamic bus sizing to 8-bits, 16-bits, 32-bits
• Burst-mode support with automatic data width adjustment
• 2 external DMA channels for external peripheral support

System Boot

• High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash
• Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending)

High-Performance 10/100 Ethernet MAC

• 10/100 Mbps MII/RMII PHY interfaces
• Full-duplex or half-duplex
• Station, broadcast, or multicast address filtering
• 2 kB RX FIFO
• 256 byte Tx FIFO with on-chip buffer descriptor ring
  • Eliminates under runs and decreases bus traffic
• Separate Tx and Rx DMA channels
• Intelligent receive-side buffer size selection
• Full statistics gathering support
• External CAM filtering support

PCI/CardBus Port

• PCI v.2.2, 32-bit bus, up to 33 MHz bus speed
• Programmable to:
  • PCI device mode
  • PCI host mode: Supports up to 3 external PCI devices (embedded PCI arbiter or externalarbiter)
  • CardBus host mode

Flexible LCD Controller

• Supports most commercially available displays
  • Active Matrix color TFT displays: Up to 24bpp direct 8:8:8 RGB;16M colors
  • Single- and dual-panel color
  • STN displays:Up to 16bpp 4:4:4 RGB;3375 colors
  • Single- and dual-panelmonochrome
  • STN displays:1, 2, 4bpp palettized gray scale
• Formats image data and generates timing control signals
• Internal programmable palette-LUT and grayscaler support different color techniques
• Programmable panel-clock frequency

USB Ports

• USB v.2.0 Full speed (12 Mbps) and Low speed (1.5 Mbps)
• Configurable to device or OHCI host
  • USB host is a bus master
  • USB device supports one bi-directional control endpoint and 11 unidirectional endpoints
• All endpoints supported by a dedicated DMA channel; 13 channels total
• 20B Rx FIFO and 20B Tx FIFO

Serial Ports

• 4 serial modules, each independently configurable to UART mode, HDLC mode, SPI Master mode, or SPI Slave mode
• Bit rates from 75 bps to 921.6 kbps: asynchronous x16 mode
• Bit rates from 1.2 kbps to 6.25 Mbps: synchronous mode
• UART provides
  • High-performance hardware and software flow control
  • Odd, even, or no parity
  • 5, 6, 7 or 8 bits
  • 1 or 2 stop bits
  • Receive-side character and buffer gap timers
• Internal or external clock support, digital PLL for Rx clock extraction
• 4 receive-side data match detectors
• 2 dedicated DMA channels per module, 8 channels total
• 32 byte Tx FIFO and 32 byte RxFIFO per module

I²C Port

• I²C v.1.0, configurable to Master or Slave mode
• Bit rates: fast (400 kHz) or normal (100 kHz) with clock stretching
• 7-bit and 10-bit address modes
• Supports I²C bus arbitration

1284 Parallel Peripheral Port

• All standard modes:
  • ECP, Byte, Nibble, Compatibility (also known as SPP or “Centronix”)
• RLE (Run Length Encoding) decoding of compressed data in ECP mode
• Operating clock from 100 kHz to 2 MHz

High Performance Multiple-Master/Distributed DMA System

• Intelligent bus bandwidth allocation (patent pending)
• System bus and peripheral bus

System Bus

• Every system bus peripheral is a bus master with a dedicated DMA engine

Peripheral Bus DMA

• One 13-channel engine supports USB device
  • 2 DMA channels support control endpoint
  • 11 DMA channels support 11 endpoints
• One 12-channel engine supports
  • 4 serial modules (8 DMA channels)
  • 1284 parallel ports (4 DMA channels)
• All DMA channels support fly-by mode

External Peripheral DMA

• One 2-channel DMA engine supports external peripheral connected to memory bus
• Each DMA channel supports memory-to-memory transfers

Power Management (Patent Pending)

• Power save during normal operation
  • Disables unused modules
• Power save during sleep mode
  • Sets memory controller to refresh
  • Disables all modules except selected wakeup modules
  • Wakeup on valid packets or characters

Vector Interrupt Controller

• Decreased bus traffic and rapid interrupt service
• Hardware interrupt prioritization

General Purpose Timers/Counters

• 16 independent 16-bit or 32-bit programmable timers or counters
  • Each has an I/O pin
• Mode selectable into:
  • Internal timer mode
  • External gated timer mode
  • External event counter
• Can be concatenated
• Resolution to measure minute-range events
• Source clock selectable: internal clock or external pulse event
• Each can be individually enabled/disabled

System Timers

• Watchdog timer
• System bus monitor timer
• System bus arbiter timer
• Peripheral bus monitor timer

General Purpose I/O

• 50 programmable GPIO pins (muxed with other functions)
• Software-readable power-up status registers for every pin for customer-defined bootstrapping

External Interrupts

• 4 external programmable interrupts
  • Rising or falling edge-sensitive
  • Low level- or high level-sensitive

Clock Generator

• Low-cost external crystal
• On-chip phase locked loop (PLL)
• Software programmable PLL parameters
• Optional external oscillator
• Separate PLL for USB

Operating Voltage

• Core: 1.5V ± 0.1V
• I/O Ring: 3.3V ± 10%

Operating Frequency

• 125 MHz: 0° C to 70° C
• 162 MHz: -40° C to 85° C
• 200 MHz: 0 °C to 70 °C

Power Consumption

• Estimated max:
  • 1.7W at 200 MHz
  • 1.4M at 162 MHz
  • 1.05W at 125 MHz
• Measured typical:
  • 950 mW at 200 MHz
  • 770 mW at 162 MHz
  • 595 mW at 125 MHz

Package

• 388-pin BGA
• 1.27 mm ball pitch
• 35 mm x 35 mm
• Lead-free; RoHS compliant

Details on ARM9 Core

• 32/16-bit Harvard RISC architecture with 5 stage pipeline (ARMv5TEJ)
• 32-bit ARM instruction set for maximum performance and flexibility
• 16-bit Thumb instruction set for increased up to 35% code density
• DSP instruction extensions and single cycle MAC
• ARM Jazelle technology, 6 CM/MHz = 1200 Caffeine Marks @ 200 MHz
• MMU which supports Windows CE and Linux
• EmbeddedICE-RT logic for real-time debug