The NS9215 NET+ARM processor is the ideal choice for every application requiring a cost-efficient 32-bit solution with high performance, strong network security and unique interface flexibility. Offering 4 KB of I-cache and D-cache and up to 150 MHz clock speed, it is designed for use in a broad range of applications such as security/access control, medical, industrial/building automation, transportation and remote monitoring.
It provides the most comprehensive list of available peripheral interfaces in the NS921x family, including an RTC with battery back-up, integrated ADC and design flexibility through additional GPIOs and complete overall interface availability. Two independent on-chip DRPIC1655X processor cores allow the software selection of a growing list of application-specific peripheral interface implementations.
A NIST-certified AES accelerator combines state-of-the-art data privacy services with superior performance, and Digi's patented dynamic power management addresses the needs of power budget conscious designs.
The easy-to-use and complete NS9215 development kit for NET+OS® is based on the field-proven ThreadX® Real-Time Operating System, and delivers a true and IPv6-ready turnkey solution. It includes the Eclipse-based Digi ESP™ IDE as well as all integrated building blocks for secure network-enabled embedded software development.
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| North America: | International: | ||
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NS9215 Development Kit for NET+OS 7 - Includes Eclipse-based Digi ESP IDE, USB debugger, Premium support package, Digi design review
View details |
NS-9215-NET |
NS-9215-NET |
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| Development Kits | North America: | International: | |
| NS9215 Development Kit for NET+OS 7 - Includes Eclipse-based Digi ESP IDE, USB debugger, Premium support package, Digi design review View details |
NS-9215-NET |
NS-9215-NET |
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| Processors | North America: | International: | |
| NS9215 - 150 MHz, 265-pin BGA, -40° C to +85° C View details |
NS9215B-0-I150 |
NS9215B-0-I150 |
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| NS9215 - 75 MHz, 265-pin BGA, -40° C to +85° C View details |
NS9215B-0-I75 |
NS9215B-0-I75 |
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| Platform | NS9210 | NS9215 |
| General | ||
| Processor | ARM926EJ-S | |
| Speed Grades | 75/150 MHz | |
| Cache | 4 KB I-cache / 4 KB D-cache | |
| Process | 0.18µ CMOS | |
| 32-bit ARMv5TEJ Instruction Set | • | |
| 16-bit Thumb Instruction Set | • | |
| MMU | • | |
| DSP Instruction Extensions | • (Improved divide, Single cycle multiply accumulate) |
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| ARM Jazelle® Java Accelerator | • | |
| Embedded ICE-RT Debug Unit | • | |
| JTAG Boundary Scan, BSDL | • | |
| Power Management Modes | • | |
| AES Accelerator | ||
| Key Length | 128-, 192-, 256-bit | |
| Cipher Modes | ECB, CBC, OFB, CTR, CCM | |
| Hardware Key Expander | • | |
| DMA-Enabled | • | |
| NIST-Compliant | • | |
| FIM (Flexible Interface Module) | ||
| FIMs | 1/2; Availability depending on application-specific use of external 16-/32-bit memory bus |
2 |
| Cores | 8-bit DRPIC1655X | |
| Speed | Up to 300 MHz (4x bus speed) | |
| Data Memory (SRAM) | 192 Bytes | |
| Program Memory (SRAM) | 2 KB | |
| Interface Options | SD/SDIO, UART, 1-Wire, CAN, USB device (low-speed), Other; Please contact us for custom interface implementation options. | |
| Power Management | ||
| Dynamic Clock Scaling (patent pending) | Full, /2, /4, /8, /16 speeds, with hardware clock scale control (wake-up events) | |
| Low-Power Sleep Modes | • | |
| Configurable Wake-Up Conditions | External IRQ, I2C, SPI, UART, Ethernet | External IRQ, I2C, SPI, UART, Ethernet, RTC |
| Disabling of Unused System Modules | • | |
| Memory Controller | ||
| Glue-less Interface | • (SDRAM, SRAM, Buffered DIMM, EEPROM, Flash) |
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| Self-Refresh (Sleep Mode) | • | |
| Dynamic/Static Memory Chip Selects | Selection of 5 | 4/4 |
| Wait States Per Memory Chip Select | 0-32 | |
| Static Memory Controller Extended Waits (EW) | Up to 16,368 | |
| Automatic Dynamic Bus Sizing | • | |
| Burst Support | 8-transfer, with automatic data width adjustment | |
| External DMA Channels | 2 | |
| System Bus DMA | ||
| High-Speed Rotating AHB arbiter | 16 channels | |
| Deterministic Bus Bandwidth Allocation | • | |
| Multiple Bus Masters | Ethernet Tx/Rx, I/O Hub, Ext DMA, ARM core | |
| External DMA | ||
| Independent DMA Channels | 2 | |
| Transfer Modes | External peripherals, External memory, AHB peripherals | |
| AES DMA Support | • | |
| AHB Master | • | |
| I/O Hub | ||
| Low Latency | • | |
| DMA | 8 channels | |
| DMA or Direct Access Mode | UART, SPI, FIM | UART, SPI, ADC, FIM |
| Direct Access Mode Only | I2C | I2C, RTC |
| AHB Master | • | |
| External Interrupts | ||
| External Programmable Interrupts | 4 | |
| Advanced Vectored Interrupt Controller | ||
| Two-Tier Priority | • (FIRQ/IRQ) |
|
| Low-Latency FIRQ | • | |
| Interrupt Sources | 32 | |
| Ethernet MAC | ||
| Data Rates | 10 / 100 Mbit/s | |
| Duplex | Full and Half | |
| PHY Interface | MII | |
| Address Filtering | Station, Broadcast, Multicast | |
| FIFO | 2 KB Rx / 256 Byes Tx | |
| Separate Tx and Rx DMA Channels | • | |
| Programmable 8-Entry Restrictive Multicast Filtering |
• | |
| Access Modes | Interrupt and DMA | |
| AHB Master | • | |
| UART | ||
| Ports | 2 / 4; Availability depending on application-specific use of external 16-/32-bit memory bus |
4 |
| Bit Rates | Up to 1.8432 Mbps | |
| Data Format | 5 to 8 data bits; Odd, Even, or No parity; 1 or 2 stop bits; MSB or LSB first | |
| Channel Modes | Normal, Local loopback, Remote loopback | |
| Modem Control Signals | RTS, CTS, DTR, DSR, DCD, RI | |
| Maskable Interrupt Conditions | Receiver idle; Transmitter idle; Receive error conditions; Character gap timeout; Character match events; State change detection: CTS, DSR, DCD, RI |
|
| FIFO | 2 KB Rx / 256 Byes Tx | |
| Transmit FIFO Bypass | • | |
| I2C v1.0 | ||
| Master/Slave | • | |
| Bit Rates | 100 kbit/s and 400 kbit/s modes | |
| Address Modes | 7-bit, 10-bit | |
| Bus Arbitration | • | |
| SPI (with Boot) | ||
| Master/Slave | • | |
| Bit Rates | 33 Mps (Master) / 7.5 Mpbs (Slave) max | |
| SPI Modes | 0, 1, 2, 3 | |
| Maskable Interrupt Conditions | • | |
| Boot Support | Serial EEPROM, High-speed ROM/flash | |
| Patent Pending Serial Boot Circuit | Automatic configuration, Internal register setup, Boot code transfer to external memory | |
| POR | ||
| 3.3V Voltage Monitoring | — | • |
| Early Power-Loss Comparator with Alert for Main Power Shutdown | — | • |
| Auxiliary Analog Comparator | — | 2.4V trip point |
| ADC | ||
| Resolution/Conversion | — | 12 bit/1 MHz |
| Multiplexed Inputs | — | Single-ended 8:1 |
| Rail-to-Rail Input Range | — | • |
| 12-Bit Output | — | DMA/Direct |
| External Reference | — | • |
| Timers/Counters/PWM | ||
| General Purpose Timers/Counters | 10 (32-bit) | |
| PWM | Up to 4 with basic or enhanced functionality | |
| Quadrature Decoder | • | |
| Software Watchdog Timer | IRQ, FIQ, RESET | |
| GPIO | ||
| Multiplexed GPIOs | Up to 54 | Up to 108 |
| Real-Time Clock | ||
| Alarm Masks and Event Detection | — | • |
| Calendar | — | 1900-2999 |
| Resolution | — | 10 ms |
| Integrated NVRAM | — | 64 Bytes |
| External Battery Backup | — | • |
| External Clock Source | — | • |
| Operating Voltage | ||
| Core | 1.8V | |
| I/O Ring | 3.3V | |
| 5V-Tolerant GPIO and Memory Inputs | • | |
| Operating Temperature | ||
| 75/150 MHz | -40° C to +85° C | |
| Power Dissipation | ||
| 150 MHz Core/75 MHz Bus | 1.019 W | |
| 75 MHz Core/75 MHz Bus | 0.828 W | |
| 112 MHz Core/56 MHz Bus | 0.638 W | |
| 56 MHz Core/56 MHz Bus | 0.499 W | |
| Sleep Mode, Wake on Ethernet | 0.073 W | |
| Sleep Mode, Wake on Ext IRQ | 0.055 W | |
| Main Power Down, Battery Draw | — | 3.0V – 32 µA; 1.8V – 6 µA |
| Package | ||
| Type | 177-pin BGA (Pin-compatible with NS7520) | 265-pin BGA |
| Ball Pitch | 0.8 mm | |
| Size | 13 x 13 mm | 15 x 15 mm |
| Lead-Free, RoHS Compliant | • | |
• Chip Feature
