Image Processing Unit (IPU)

The Image Processing Unit (IPU) is designed to support video and graphics processing functions and to interface with video and still image sensors and displays.

The IPU driver provides the following software support:

• Synchronous frame buffer driver
• Display Interface (DI)
• Display Processor (DP)
• Image DMA Controller (IDMAC)
• CMOS Sensor Interface (CSI)
• Image Converter (IC)

Kernel configuration

You can manage the IPU driver support through the kernel configuration option:

• Image Processing Unit Driver (CONFIG_MXC_IPU)

This option is enabled as built-in on the default ConnectCore 6 SBC kernel configuration file.

Platform driver mapping

The IPU drivers for the i.MX6 are located at drivers/mxc/ipu3:

File	Description
ipu_common.c	IPU common library functions
ipu_ic.c	IPU IC base driver
ipu_device.c	IPU driver device interface and fops functions
ipu_capture.c	IPU CSI capture base driver
ipu_disp.c	IPU display functions
ipu_calc_stripes_sizes.c	Multi-stripes method functions for ipu_device.c
vdoa.c	VDOA post-processing driver, used by ipu_device.c

drivers/video/mxc:

File	Description
mxc_ipuv3_fb.c	Driver for synchronous frame buffer
mxc_hdmi.c	Display driver for HDMI interface
ldb.c	Driver for synchronous frame buffer for on chip LVDS
mxc_dispdrv.c	Display driver framework for synchronous frame buffer
mxc_edid.c	Driver for EDID

Device tree bindings and customization

The i.MX6 IPU device tree binding is documented at Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt.

The IPU is defined in the i.MX6 CPU and ConnectCore 6 SBC device tree files.

Definition of the GPU interface

Common i.MX6 device tree

ipu1: ipu@02400000 {
            compatible = "fsl,imx6q-ipu";
            reg = <0x02400000 0x400000>;
            interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
                     <0 5 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&clks IMX6QDL_CLK_IPU1>,
                 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
                 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
                 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
            clock-names = "bus",
                      "di0", "di1",
                      "di0_sel", "di1_sel",
                      "ldb_di0", "ldb_di1";
            resets = <&src 2>;
            bypass_reset = <0>;
};

IOMUX configuration

Since the IPU is an internal CPU device, it doesn't have an IOMUX configuration.