The parallel video connects the LCD-TFT display controller (LTDC) to an external connector.

Kernel configuration

You can manage the parallel driver support through the kernel configuration option:

  • STM LCD controller driver (CONFIG_DRM_STM)

This option is enabled as built-in on the ConnectCore MP15 kernel configuration file.

Platform driver mapping

The LCD drivers are located at:

File Description

drivers/gpu/drm/stm/drv.c

LCD display driver

Device tree bindings and customization

The LCD interface device tree binding is documented at Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml.

The ConnectCore MP15 Development Kit device tree has support for Fusion 7" LCD display:

ConnectCore MP15 Development Kit device tree
panel {
	compatible = "tpk,f07a-0102";
	power-supply = <&v3v3>;
	backlight = <&display_bl>;

	port {
		panel_in: endpoint {
			remote-endpoint = <&ltdc_ep0_out>;
		};
	};
};
Fusion 7" display is disabled by default because the many parallel LCD lines are also multiplexed with other functionality. See Enable parallel LCD and disable conflicting interfaces for instructions on enabling the parallel display.

IOMUX configuration

The ConnectCore MP15 Development Kit device tree contains two different pinctrl configurations for the LCD pads:

  • 24-bit with only MSB 18-bit data LCD, for displays that only support 18-bits (RGB666)

  • 24-bit LCD, for displays that support 24-bits (RGB888)

ConnectCore MP15 Development Kit device tree
&pinctrl {
	ccmp15_ltdc_18_bits_pins: ltdc-18bits-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G',  7, AF14)>, /* LCD_CLK */
				 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
				 <STM32_PINMUX('I',  9, AF14)>, /* LCD_VSYNC */
				 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
				 <STM32_PINMUX('H',  8, AF14)>, /* LCD_R2 */
				 <STM32_PINMUX('B',  0,  AF9)>, /* LCD_R3 */
				 <STM32_PINMUX('A',  5, AF14)>, /* LCD_R4 */
				 <STM32_PINMUX('C',  0, AF14)>, /* LCD_R5 */
				 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
				 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
				 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
				 <STM32_PINMUX('G', 10,  AF9)>, /* LCD_G3 */
				 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
				 <STM32_PINMUX('F', 11, AF14)>, /* LCD_G5 */
				 <STM32_PINMUX('I', 11,  AF9)>, /* LCD_G6 */
				 <STM32_PINMUX('B',  5, AF14)>, /* LCD_G7 */
				 <STM32_PINMUX('A',  3,  AF9)>, /* LCD_B2 */
				 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
				 <STM32_PINMUX('I',  4, AF14)>, /* LCD_B4 */
				 <STM32_PINMUX('I',  5, AF14)>, /* LCD_B5 */
				 <STM32_PINMUX('I',  6, AF14)>, /* LCD_B6 */
				 <STM32_PINMUX('I',  7, AF14)>; /* LCD_B7 */
			bias-disable;
			drive-push-pull;
			slew-rate = <1>;
		};
		pins2 {
			pinmux = <STM32_PINMUX('H',  2, GPIO)>, /* LCD_R0 */
				 <STM32_PINMUX('H',  3, GPIO)>, /* LCD_R1 */
				 <STM32_PINMUX('B',  1, GPIO)>, /* LCD_G0 */
				 <STM32_PINMUX('E',  6, GPIO)>, /* LCD_G1 */
				 <STM32_PINMUX('E',  4, GPIO)>, /* LCD_B0 */
				 <STM32_PINMUX('G', 12, GPIO)>; /* LCD_B1 */
			bias-pull-down;
			drive-push-pull;
			slew-rate = <0>;
		};
	};

	ccmp15_ltdc_24_bits_pins: ltdc-24bits-0 {
		pins {
			pinmux = <STM32_PINMUX('G',  7, AF14)>, /* LCD_CLK */
				 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
				 <STM32_PINMUX('I',  9, AF14)>, /* LCD_VSYNC */
				 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
				 <STM32_PINMUX('H',  2, AF14)>, /* LCD_R0 */
				 <STM32_PINMUX('H',  3, AF14)>, /* LCD_R1 */
				 <STM32_PINMUX('H',  8, AF14)>, /* LCD_R2 */
				 <STM32_PINMUX('B',  0,  AF9)>, /* LCD_R3 */
				 <STM32_PINMUX('A',  5, AF14)>, /* LCD_R4 */
				 <STM32_PINMUX('C',  0, AF14)>, /* LCD_R5 */
				 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
				 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
				 <STM32_PINMUX('B',  1, AF14)>, /* LCD_G0 */
				 <STM32_PINMUX('E',  6, AF14)>, /* LCD_G1 */
				 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
				 <STM32_PINMUX('G', 10,  AF9)>, /* LCD_G3 */
				 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
				 <STM32_PINMUX('F', 11, AF14)>, /* LCD_G5 */
				 <STM32_PINMUX('I', 11,  AF9)>, /* LCD_G6 */
				 <STM32_PINMUX('B',  5, AF14)>, /* LCD_G7 */
				 <STM32_PINMUX('E',  4, AF14)>, /* LCD_B0 */
				 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
				 <STM32_PINMUX('A',  3,  AF9)>, /* LCD_B2 */
				 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
				 <STM32_PINMUX('I',  4, AF14)>, /* LCD_B4 */
				 <STM32_PINMUX('I',  5, AF14)>, /* LCD_B5 */
				 <STM32_PINMUX('I',  6, AF14)>, /* LCD_B6 */
				 <STM32_PINMUX('I',  7, AF14)>; /* LCD_B7 */
			bias-disable;
			drive-push-pull;
			slew-rate = <1>;
		};
	};

	ccmp15_ltdc_sleep_pins: ltdc-sleep-0 {
		pins {
			pinmux = <STM32_PINMUX('G',  7, ANALOG)>, /* LCD_CLK */
				 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
				 <STM32_PINMUX('I',  9, ANALOG)>, /* LCD_VSYNC */
				 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
				 <STM32_PINMUX('H',  2, ANALOG)>, /* LCD_R0 */
				 <STM32_PINMUX('H',  3, ANALOG)>, /* LCD_R1 */
				 <STM32_PINMUX('H',  8, ANALOG)>, /* LCD_R2 */
				 <STM32_PINMUX('B',  0, ANALOG)>, /* LCD_R3 */
				 <STM32_PINMUX('A',  5, ANALOG)>, /* LCD_R4 */
				 <STM32_PINMUX('C',  0, ANALOG)>, /* LCD_R5 */
				 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
				 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
				 <STM32_PINMUX('B',  1, ANALOG)>, /* LCD_G0 */
				 <STM32_PINMUX('E',  6, ANALOG)>, /* LCD_G1 */
				 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
				 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_G3 */
				 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
				 <STM32_PINMUX('F', 11, ANALOG)>, /* LCD_G5 */
				 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
				 <STM32_PINMUX('B',  5, ANALOG)>, /* LCD_G7 */
				 <STM32_PINMUX('E',  4, ANALOG)>, /* LCD_B0 */
				 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
				 <STM32_PINMUX('A',  3, ANALOG)>, /* LCD_B2 */
				 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
				 <STM32_PINMUX('I',  4, ANALOG)>, /* LCD_B4 */
				 <STM32_PINMUX('I',  5, ANALOG)>, /* LCD_B5 */
				 <STM32_PINMUX('I',  6, ANALOG)>, /* LCD_B6 */
				 <STM32_PINMUX('I',  7, ANALOG)>; /* LCD_B7 */
		};
	};
};

Enable parallel LCD and disable conflicting interfaces

The parallel LCD display is disabled by default because many parallel LCD lines are also multiplexed with other functionality. To enable it, you must enable the panel node and disable the conflicting interfaces on your device tree:

  • USART3

  • LT8912

  • DSI

Digi provides a pre-compiled device tree overlay that does exactly this so you can test the parallel LCD interface on a Fusion 7" display without needing to recompile a device tree. To apply this overlay, run the following command in U-Boot:

=> setenv overlays _ov_board_fusion7-parallel_ccmp15-dvk.dtbo