ConnectCore for i.MX6UL MCA ADC channel assignment

Question

I apologize for the silly question if I have overlooked something but I am looking for documentation outlining the MCA_IO pin number to the cciMX6ULsbc ADC channel number.

I see that in dey 2.0-r5 support was added for the iMX6UL ADC channels. I currently have the Digi ConnectCore 6UL Development Kit which according to the documentation supports five ADC channels on the following Microcontroller Assist (MCA) IO pins: MCA_IO0, MCA_IO1, MCA_IO3, MCA_IO4, and MCA_IO5.

I am looking to test the ADCs on my developments kit and I want to know the channel mapping from the MCA_IO pin to the ADC channel mapping in arch/arm/boot/dts/imx6ul-ccimx6ulsbc-id135.dts. I am assuming it is not 1 to 1 because the default channels are 2,3, and 5 in that file but I could be wrong. Any guidance or documentation would be greatly appreciated.

Answer 1

Thanks for the update I received the answer I was looking for from support:

Via the MCA you provided 5 ADC channels, 2 of which are used internally by the SBC.

MCA_IO0 - used by SBC
MCA_IO1 - accessible via connector J30_pin7 (GPIO connector)
MCA_IO3 - accessible via connector J30_pin8 (GPIO connector)
MCA_IO4 - used by SBC
MCA_IO5 - accessible via connector J34_pin6 (SPI connector)

Enabling these channels in the device tree is done by adding the following to your platform’s .dts file.

# enable ADC channels 1, 3, 5
&mca_adc {
digi,adc-ch-lit = <1 3 5>;
digi,adc-vref = <300000>;
};

Answer 2

The DTS for R5 can be found here:
https://github.com/digi-embedded/linux/blob/v4.1/dey-2.0/maint/arch/arm/boot/dts/imx6ul-ccimx6ulsbc-id135.dts

looks like ADC is disabled by default, but is this what you are looking for:
/*
* Uncomment to enable the i.MX6UL SoC ADCs.
* Include in adc-ch-list the ADC channels (from 0 to 9) that you want to
* enable. Note that the iomux has to be configured accordingly in pinctrl_adc1
* to configure the pad for ADC operation
*/
//&adc1 {
// pinctrl-names = "default";
// pinctrl-0 = <&pinctrl_adc1>;
// adc-ch-list = <2 3 5>;
// status = "okay";
//};

.....

/* Pin mux configuration */
&iomuxc {
imx6ul-ccimx6ul {
/* Uncomment specific pins of the ADC channels enabled in 'adc-ch-list' */
//pinctrl_adc1: adc1grp {
// fsl,pins = <
// /* EXP_GPIO_1 -> GPIO1_5/ADC1_IN5 */
// MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0
// /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
// MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
// /* EXP_GPIO_3 -> GPIO1_2/ADC1_IN2 */
// MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
// >;
//};
};
};