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How do I set up TLB in MMU on 9p9215 for memory mapped I/O?

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I'm porting an application from a 7u 7520 module to a 9p 9215 module. It uses memory mapped I/O to access an FPGA. There's no MMU on the 7u, so as part of the port I need to add code to set up the MMU. I customized the code for CS3 in connectcore9p9215_a/cs.c to set up the Memory controller and to set the Base and Mask registers. I have read the MMU section of the 9p9215 Hardware Reference, but I could really use some sample code that sets up the MMU. The FPGA has 8 address bits and 8 data bits, so a 1KB page would be big enought.
asked Mar 22, 2021 in Embedded Devices by cjwilde New to the Community (0 points)

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1 Answer

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* MMU Definition Table
* You should edit this table to reflect the address map of your application.
* The BSP processes this table at startup to build the MMU address
* translation table. This table determines the access level and caching
* options for each section of memory.
* Each entry in this table specifies a section of the processor's address space
* and sets the MMU options for it. Any sections of memory that do not have
* an entry in this table are defined as nonaccessable. Any attempt to access
* such a region will cause an abort exception.
* The NASetCacheAccessModes() function can be used to modify the cache and user
* access settings for a region of memory after the MMU address translation table
* has been setup. The page size for regions set in this table cannot be
* modified at runtime.
* Refer to the documentation on mmuTableType for details on how to create
* entries.
* @external
* @category MMU
* @since 6.1
* @note Use large page sizes to improve performance.
* The MMU has a small internal cache of MMU table
* entries. As long as the table entry for the memory being accessed is
* inside the MMU's internal cache, the MMU does not have to scan the
* MMU table in RAM. However, whenever the CPU accesses memory whose
* table entry is not already in the MMU's cache, the MMU has to look up the
* table entry in RAM. This incurs at least one extra memory access
* (more for coarse sections) for the access. The more table entries
* there are, the more likely this is to happen.
* @see @link mmuCacheModeValues
* @see @link mmuUserAccessValues
* @see @link mmuPageSizes
* @see @link mmuTableType
* @see @link NASetCacheAccessModes
mmuTableType mmuTable[] =
/* Start End Page Size Cache Mode User Access Physical Address */
/* ========== ========== ================ ============= =========== =============== */
{0x00000000, 0x00ffffff, MMU_PAGE_SIZE_1M, MMU_WRITE_BACK, MMU_CLIENT_RW, 0x00000000, 0x00ffffff}, /* 16 Megs of RAM */
{0xC0000000, 0xC0ffffff, MMU_PAGE_SIZE_1M, MMU_BUFFERED, MMU_CLIENT_RW, 0x00000000, 0x00ffffff} /* Uncached SDRAM */

Just add an entry to that table.
answered Mar 23, 2021 by LeonidM Veteran of the Digi Community (4,411 points)