The Image Processing Unit (IPU) is designed to support video and graphics processing functions and to interface with video and still image sensors and displays.

The IPU driver provides the following software support:

  • Synchronous frame buffer driver

  • Display Interface (DI)

  • Display Processor (DP)

  • Image DMA Controller (IDMAC)

  • CMOS Sensor Interface (CSI)

  • Image Converter (IC)

Kernel configuration

You can manage the IPU driver support through the kernel configuration option:

  • Image Processing Unit Driver (CONFIG_MXC_IPU)

This option is enabled as built-in on the ConnectCore 6 kernel configuration file.

Kernel driver

The IPU drivers for the i.MX6 are located at drivers/mxc/ipu3:

File Description

ipu_common.c

IPU common library functions

ipu_ic.c

IPU IC base driver

ipu_device.c

IPU driver device interface and fops functions

ipu_capture.c

IPU CSI capture base driver

ipu_disp.c

IPU display functions

ipu_calc_stripes_sizes.c

Multi-stripes method functions for ipu_device.c

vdoa.c

VDOA post-processing driver, used by ipu_device.c

drivers/video/mxc:

File Description

mxc_ipuv3_fb.c

Driver for synchronous frame buffer

mxc_hdmi.c

Display driver for HDMI interface

ldb.c

Driver for synchronous frame buffer for on chip LVDS

mxc_dispdrv.c

Display driver framework for synchronous frame buffer

mxc_edid.c

Driver for EDID

Device tree bindings and customization

The i.MX6 IPU device tree binding is documented at Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt.

The IPU is defined in the i.MX6 CPU and ConnectCore 6 SBC device tree files.

Definition of the GPU interface

Common ConnectCore 6 device tree
ipu1: ipu@02400000 {

	#address-cells = <1>;
	#size-cells = <0>;

	compatible = "fsl,imx6q-ipu";
	reg = <0x02400000 0x400000>;
	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
		     <0 5 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPU1>,
		 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
	clock-names = "bus",
		      "di0", "di1",
		      "di0_sel", "di1_sel",
		      "ldb_di0", "ldb_di1";
	resets = <&src 2>;
	bypass_reset = <0>;
};

IOMUX configuration

Since the IPU is an internal CPU device, it doesn’t have an IOMUX configuration.

HDMI video

The High Definition Multimedia Interface (HDMI) driver supports the on-chip DesignWare HDMI hardware module. This module allows you to transfer uncompressed video, audio, and data using a single cable.

The ConnectCore 6 SBC includes an HDMI transmitter port connected to I2C3.

This section covers HDMI video. For HDMI audio interface documentation, see HDMI audio.

Kernel configuration

You can manage the HDMI driver support through the kernel configuration option:

  • MXC HDMI driver support (CONFIG_FB_MXC_HDMI)

This option is enabled as built-in on the ConnectCore 6 kernel configuration file.

Additionally, the BSP has a driver for Consumer Electronic Control (CEC). You can manage the HDMI CEC driver support through the kernel configuration option MXC HDMI CEC (Consumer Electronic Control) support (CONFIG_MXC_HDMI_CEC), disabled on the ConnectCore 6 kernel configuration file.

This feature is not supported in Digi Embedded Yocto.

Platform driver mapping

The HDMI drivers for the i.MX6 are located at:

File Description

drivers/mfd/mxc-hdmi-core.c

HDMI core driver

drivers/video/mxc/mxc_hdmi.c

HDMI display driver

drivers/mxc/mxc_hdmi-cec.c

HDMI CEC driver

Device tree bindings and customization

The i.MX6 HDMI interface device tree binding is documented at Documentation/devicetree/bindings/video/mxc_hdmi_video.txt.

The HDMI interface is defined in the i.MX6 CPU and ConnectCore 6 SBC device tree files.

Definition of the HDMI video interface

Common ConnectCore 6 device tree
hdmi_core: hdmi_core@00120000 {
	compatible = "fsl,imx6q-hdmi-core";
	reg = <0x00120000 0x9000>;
	clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
		 <&clks IMX6QDL_CLK_HDMI_IAHB>,
		 <&clks IMX6QDL_CLK_HSI_TX>;
	clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
	status = "disabled";
};
hdmi_video: hdmi_video@020e0000 {
	compatible = "fsl,imx6q-hdmi-video";
	reg = <0x020e0000 0x1000>;
	reg-names = "hdmi_gpr";
	interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
		 <&clks IMX6QDL_CLK_HDMI_IAHB>,
		 <&clks IMX6QDL_CLK_HSI_TX>;
	clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
	status = "disabled";
};

IOMUX configuration

The HDMI uses dedicated pins. No IOMUX configuration is necessary.

HDMI IPU:DI selection and video enabling

You can configure HDMI video to originate from either of the two Display Interface ports (DI0 or DI1) within any IPU in the i.MX6 CPU.

ConnectCore 6 SBC device tree
&hdmi_core {
	ipu_id = <1>;
	disp_id = <1>;
	status = "okay";
};
&hdmi_video {
	fsl,phy_reg_vlev = <0x0294>;
	fsl,phy_reg_cksymtx = <0x800d>;
	status = "okay";
};

HDMI transmitter port on I2C3

ConnectCore 6 SBC device tree
&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	hdmi: edid@50 {
		compatible = "fsl,imx6-hdmi-i2c";
		reg = <0x50>;
	};

	[...]
};

HDMI resolution

Specify HDMI display resolution on your platform’s device tree using the frame buffer property mode_str:

mxcfb1: fb@0 {
	compatible = "fsl,mxc_sdc_fb";
	disp_dev = "hdmi";
	interface_pix_fmt = "RGB24";
	mode_str ="1920x1080M@60";
	default_bpp = <32>;
	int_clk = <0>;
	late_init = <0>;
	status = "okay";
};

You can overwrite the device tree configuration through the video kernel command line argument passed by the U-Boot bootloader. Use the variable extra_bootargs to append parameters to the kernel command line. For example, to set the HDMI resolution on frame buffer 0 to 1280x720 pixels with a refresh rate of @60Hz, run the following command on the U-Boot console:

=> setenv extra_bootargs video=mxcfb0:dev=hdmi,1280x720M@60 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off

To discover the available modes supported by your monitor, run the following command:

~# cat /sys/class/graphics/fb0/modes
U:640x480p-59
S:640x480p-60
S:720x480p-60
S:720x480p-60
S:1280x720p-60
S:1920x1080p-60
S:720x576p-50
S:720x576p-50
S:1280x720p-50
S:1920x1080p-50
V:640x480p-60
D:1920x1080p-60
V:640x480p-60

CEA modes and DVI support

By default, the HDMI driver allows only CEA modes. The HDMI interface is able to support both audio and video using CEA modes. However, particularly when using DVI displays, you may want to use non-CEA modes. In those cases, you can enable all non-CEA modes by running the following command on the U-Boot console:

=> setenv extra_bootargs mxc_hdmi.only_cea=0
Non-CEA modes configure the HDMI interface with clock rates that are not valid for audio support.

When using HDMI to DVI adapters, you may need to remove the HDMI capabilities from the EDID settings. To do so, use the dvi_mode configuration entry as follows:

ConnectCore 6 SBC device tree
&hdmi_video {
	fsl,phy_reg_vlev = <0x0294>;
	fsl,phy_reg_cksymtx = <0x800d>;
	digi,dvi_mode;
	status = "okay";
};

LVDS display bridge

The LVDS Display Bridge (LDB) connects the Image Processing Unit (IPU) to an external LVDS display interface.

The ConnectCore 6 SBC contains two LVDS display connectors.

Kernel configuration

You can manage the LDB driver support through the kernel configuration option:

  • MXC LDB (CONFIG_FB_MXC_LDB)

This option is enabled as built-in on the ConnectCore 6 kernel configuration file.

Platform driver mapping

The HDMI drivers for the i.MX6 are located at:

File Description

drivers/video/mxc/ldb.c

LDB display driver

Device tree bindings and customization

The i.MX6 LDB interface device tree binding is documented at Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt.

The LDB interface is defined in the i.MX6 CPU and ConnectCore 6 SBC device tree files.

IOMUX configuration

The LVDS interfaces use dedicated pins. No IOMUX configuration is necessary.

LVDS channels

ConnectCore 6 SBC device tree
&ldb {
	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;

		display-timings {
			native-mode = <&g101evn010_1>;

			/* Fusion 10" F10A-0102 */
			hsd101pfw2_1: timing@0 {
				clock-frequency = <45000000>;
				hactive = <1024>;
				vactive = <600>;
				hfront-porch = <0>;
				hback-porch = <0>;
				hsync-len = <176>;
				vback-porch = <0>;
				vfront-porch = <0>;
				vsync-len = <25>;
			};

			/* AUO G101EVN01.0 */
			g101evn010_1: timing@1 {
				clock-frequency = <68930000>;
				hactive = <1280>;
				vactive = <800>;
				hfront-porch = <120>;
				hback-porch = <0>;
				hsync-len = <8>;
				vback-porch = <10>;
				vfront-porch = <0>;
				vsync-len = <6>;
				hsync-active = <1>;
				vsync-active = <1>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
	lvds-channel@1 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;

		display-timings {
			native-mode = <&g101evn010_2>;

			/* Fusion 10" F10A-0102 */
			hsd101pfw2_2: timing@0 {
				clock-frequency = <45000000>;
				hactive = <1024>;
				vactive = <600>;
				hfront-porch = <0>;
				hback-porch = <0>;
				hsync-len = <176>;
				vback-porch = <0>;
				vfront-porch = <2>;
				vsync-len = <23>;
			};

			/* AUO G101EVN01.0 */
			g101evn010_2: timing@1 {
				clock-frequency = <68930000>;
				hactive = <1280>;
				vactive = <800>;
				hfront-porch = <120>;
				hback-porch = <0>;
				hsync-len = <8>;
				vback-porch = <10>;
				vfront-porch = <0>;
				vsync-len = <6>;
				hsync-active = <1>;
				vsync-active = <1>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
};

On the ConnectCore 6 SBC device tree, two LVDS displays are declared inside each lvds-channel node:

  • Fusion 10" LVDS (hsd101pfw2)

  • AUO 10" LVDS (g101evn010)

The property native-mode inside display-timings selects which of the defined displays on the device tree is enabled. On the ConnectCore 6 SBC, the default selected display is the AUO 10". To switch to the Fusion display, see Enable support for a Fusion display.

LVDS as primary display

The default ConnectCore 6 SBC device tree establishes the HDMI video interface as primary display (on frame buffer 0). This configuration can be overridden through the video kernel command line argument passed by the bootloader.

For example, to enable the LVDS on frame buffer 0, append the following to U-Boot environment variable extra_bootargs:

=> setenv extra_bootargs $extra_bootargs video=mxcfb0:dev=ldb,if=RGB666 video=mxcfb1:dev=hdmi,1920x1080M@60
=> saveenv

Parallel LCD display

The parallel video connects the Image Processing Unit (IPU) to an external parallel LCD video interface.

Kernel configuration

You can manage the LDB driver support through the kernel configuration option:

  • LCD PLATFORM (CONFIG_LCD_PLATFORM)

This option is enabled as built-in on the ConnectCore 6 kernel configuration file.

Platform driver mapping

The LCD drivers are located at:

File Description

drivers/video/fbdev/mxc/mxc_lcdif.c

LCD display driver

Device tree bindings and customization

The LCD interface device tree binding is documented at Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt.

The Parallel video interface is defined in the SBC device tree files.

IOMUX configuration

Parallel video interface IOMUX configuration:

&iomuxc {
	ipu1 {
		/* Parallel display */
		pinctrl_ipu1_di0: ipu1grp-2 {
			fsl,pins = <
				/* DISP0_CLK */
				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
				/* DISP0_DRDY */
				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
				/* Data bus */
				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
			>;
		};
	};
};

Enable parallel LCD and disable conflicting interfaces

The parallel LCD display is disabled by default since some of the pads it uses are also multiplexed with other functionality. Enable the lcd node and disable the following conflicting interfaces on your device tree:

  • MIPI display

  • PWM1

@@ -55,9 +55,9 @@
  * IPU0:DI0 with MIPI display: comment the 'mipi_dsi' and 'mipi_dsi_reset' nodes.
  * Pad DISP0_DAT8 with PWM1: comment the 'pwm1' node.
  */
-//&lcd {
-//     status = "okay";
-//};
+&lcd {
+       status = "okay";
+};

 &ldb {
        status = "okay";
@@ -158,13 +158,13 @@
 /*
  * The MIPI display conflicts with IPU0:DI0 on the parallel LCD.
  */
-&mipi_dsi {
-       status = "okay";
-};
+// &mipi_dsi {
+//     status = "okay";
+// };

-&mipi_dsi_reset {
-       status = "okay";
-};
+// &mipi_dsi_reset {
+//     status = "okay";
+// };

 &pcie {
        status = "okay";
@@ -174,9 +174,9 @@
  * PWM1 uses pad DISP0_DAT8 on pin 10 of the parallel LCD connector.
  * Disable PWM1 if you want to use the parallel LCD.
  */
-&pwm1 {
-       status = "okay";
-};
+// &pwm1 {
+//     status = "okay";
+// };

 &ssi2 {
        status = "okay";

Display timings

The LCD driver doesn’t support display timings from the device tree, so the timings must be hardcoded in a database array in the driver itself. Specify LCD display timings in your platform’s device tree using the frame buffer property mode_str:

mxcfb3: fb@2 {
	compatible = "fsl,mxc_sdc_fb";
	disp_dev = "lcd";
	interface_pix_fmt = "RGB666";
	mode_str ="FUSION7";
	default_bpp = <16>;
	int_clk = <0>;
	late_init = <0>;
	status = "disabled";
};

LCD as primary display

The default device tree establishes the HDMI video interface as the primary display (on frame buffer 0). This configuration can be overridden through the video kernel command line argument passed by the bootloader.

For example, to enable the LCD on frame buffer 0, append the following to U-Boot environment variable extra_bootargs:

=> setenv extra_bootargs $extra_bootargs video=mxcfb0:dev=lcd,mode_str=FUSION7 video=mxcfb1:dev=hdmi,1920x1080M@60
=> saveenv

Touch screen

The ConnectCore 6 SBC supports external capacitive touch controller for Fusion 7" and AUO 10" LCD displays, connected through the I2C3 port.

For example, to enable the touch support for the parallel LCD display, uncomment the following lines in the device tree:

&i2c3 {
	fusion@14 {
		compatible = "touchrev,fusion-touch";
		reg = <0x14>;
		/* Interrupt for parallel LCD */
		interrupt-parent = <&gpio2>;
		interrupts = <1 1>;
		status = "okay";
	};
};