Pulse-width modulation (PWM) is a technique that modifies the duty-cycle of a pulsing signal to encode information or to control the amount of energy provided to a charge.

On the ConnectCore 8M Nano system-on-module:

  • Four PWM signals (from PWM1 to PWM4) are available from the {cpu-family} system-on-chip (multiplexed with other signals).

On the ConnectCore 8M Nano Development Kit:

  • PWM1 is available at EXP_I2C_SDA on the J48 expansion connector. PWM1 is disabled by default due to conflicts with I2C4.

  • PWM2, PWM3, and PWM4 are connected to the J46 expansion connector on pins 7, 9, and 4 respectively.

This chapter describes the PWM channels from the CPU. See MCA Pulse Width Modulation (PWM) for information about the MCA PWM controllers.

Kernel configuration

You can manage the {cpu-family} PWM driver support through the following kernel configuration option:

  • i.MX27 PWM support (CONFIG_PWM_IMX27)

This option is enabled as built-in on the default ConnectCore 8M Nano kernel configuration file.

Kernel driver

The driver for the {cpu-family} PWM is located at:

File Description


PWM driver

Device tree bindings and customization

The {cpu-family} PWM interface is documented at Documentation/devicetree/bindings/pwm/imx-pwm.txt.

{cpu-family} PWM interfaces

The common {cpu-family} CPU device tree file contains entries for all the PWM channels:

{cpu-family} device tree
	pwm1: pwm@30660000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30660000 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
			 <&clk IMX8MN_CLK_PWM1_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";

	pwm2: pwm@30670000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30670000 0x10000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
			 <&clk IMX8MN_CLK_PWM2_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";

	pwm3: pwm@30680000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30680000 0x10000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
			 <&clk IMX8MN_CLK_PWM3_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";

	pwm4: pwm@30690000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30690000 0x10000>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
			 <&clk IMX8MN_CLK_PWM4_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";

IOMUX configuration

You must configure the pads that are to be used as {cpu-family} PWMs. See Pin multiplexing (IOMUX).

{cpu-family} pads should only have one IOMUX configuration. Remove other configurations for those pads, like GPIO, when configuring them as PWMs.

The default device tree enables PWM2, PWM3, and PWM4, available on the ConnectCore 8M Nano Development Kit J46 expansion connector:

  • PWM2 corresponds to pad GPIO1_IO13

  • PWM3 corresponds to pad GPIO1_IO14

  • PWM4 corresponds to pad GPIO1_IO15

Depending on the frequency of the PWM signal and the hardware around it, you must carefully select the pad settings (the numerical values following the IOMUX definition on the device tree). See Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt for information about the different values. Also see the NXP application note AN5078 Influence of pin setting on system function and performance for additional information.

Using the PWM channels

Control PWM signal from sysfs

Each PWM interface is registered in the system as a standalone PWM controller.

The PWM interfaces appear under /sys/class/pwm:

# ls /sys/class/pwm/
pwmchip0  pwmchip6  pwmchip7  pwmchip8

The PWM interfaces begin numbering with an index of 0. The indexes are calculated using the number of channels of the previous interface. On the example above:

  • MCA PWM0 chip 4 (6 channels) is pwmchip0

  • {cpu-family} PWM2 (1 channel) is pwmchip6

  • {cpu-family} PWM3 (1 channel) is pwmchip7

  • {cpu-family} PWM4 (1 channel) is pwmchip8

Each CPU PWM interface only manages one PWM signal. Check the number of channels of an interface by printing the value of npwm:

# cat /sys/class/pwm/pwmchip6/npwm

To access one channel of a PWM interface, export the channel index (0 since there is only one):

# echo 0 > /sys/class/pwm/pwmchip6/export
You won’t be able to request PWM channels that are in use by other drivers, like those used by the backlight.

Now you can access the PWM channel and configure its settings:

# ls /sys/class/pwm/pwmchip6/pwm0/
duty_cycle  enable      period      polarity    power       uevent

Period and duty cycle must be given in nanoseconds. For example, to configure a 100kHz signal with 20% duty cycle:

# echo 10000 > /sys/class/pwm/pwmchip6/pwm0/period
# echo 2000 > /sys/class/pwm/pwmchip6/pwm0/duty_cycle

To enable the PWM signal:

# echo 1 > /sys/class/pwm/pwmchip6/pwm0/enable

The default polarity is normal (active high for the duty cycle). To invert the polarity:

# echo inversed > /sys/class/pwm/pwmchip6/pwm0/polarity

Using Digi APIx library from a C application

An example application called apix-pwm-example is included in the dey-examples-digiapix recipe (part of dey-examples package) of meta-digi layer. This application shows how to generate a PWM signal using Digi APIx library on the ConnectCore 8M Nano platform.

Go to GitHub to see the application instructions and source code.

See PWM API for more information about the PWM APIx.