The NXP i.MX8M Nano CPU provides a set of one-time programmable bits (eFuses) structured as 15 banks. Each bank is composed of four words of 32 bits each.

These bits can be blown just once. Programming them is an irreversible operation.

Kernel configuration

You can manage the OTP driver support through the kernel configuration option:

  • Freescale On-Chip OTP Memory Support (CONFIG_FSL_OTP)

This option gives you read-only access to the OTP bits and is enabled as built-in on the ConnectCore 8M Nano Development Kit kernel configuration file.

OTP memory write access is not yet supported on Linux.

Kernel driver

The OTP memory driver is located at:

File Description


Freescale On-Chip OTP driver

Device tree bindings

The i.MX8M Nano OTP memory driver device tree binding is documented at Documentation/devicetree/bindings/nvmem/imx-ocotp.txt.

i.MX8M Nano device tree
ocotp: ocotp-ctrl@30350000 {
	compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
	reg = <0 0x30350000 0 0x10000>;
	clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
	/* For nvmem subnodes */
	#address-cells = <1>;
	#size-cells = <1>;

OTP user space usage

The OTP words are accessible through the sysfs at /sys/fsl_otp.

Read access

Use the cat command to read each word:

The HW_OCOTP_MAC_ADDR0, HW_OCOTP_MAC_ADDR1, and HW_OCOTP_MAC_ADDR2 words are reserved by Digi to program the module’s Hardware ID. (MAC addresses are programmed in the U-Boot environment.)