The NXP {cpu-family} CPU has two 10/100 Ethernet MACs.

On the ConnectCore 6UL SBC Express:

  • Ethernet1 port is connected to a 10/100 Microchip LAN8720a PHY

On the ConnectCore 6UL SBC Pro:

  • Ethernet1 port is connected to a 10/100 Microchip LAN8720a PHY.

  • Ethernet2 port is connected to a 10/100 Microchip LAN8720a PHY.

Kernel configuration

You can manage the Ethernet driver and PHY Device support through the following kernel configuration options:

  • FEC Ethernet controller (of ColdFire and some i.MX CPUs) (CONFIG_FEC)

  • PHY device support for LAN83C185, LAN8187 and LAN8700 (CONFIG_SMSC_PHY)

These options are enabled as built-in on the default ConnectCore 6UL kernel configuration file.

Kernel driver

The driver for the Ethernet interface is located at:

File Description

drivers/net/ethernet/freescale/fec_main.c

i.MX FEC driver

drivers/net/phy/smsc.c

Driver for Microchip LAN8720a PHY

Device tree bindings and customization

The {cpu-family} Ethernet interface device tree binding is documented at Documentation/devicetree/bindings/net/fsl-fec.txt. The Ethernet interfaces are defined in the {cpu-family} CPU, ConnectCore 6UL SBC Express, and ConnectCore 6UL SBC Pro device tree files.

Example: FEC1 & FEC2 on ConnectCore 6UL SBC Pro

Definition of the FECs

{cpu-family} device tree
fec1: ethernet@02188000 {
	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	reg = <0x02188000 0x4000>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ENET>,
		    <&clks IMX6UL_CLK_ENET_AHB>,
		    <&clks IMX6UL_CLK_ENET_PTP>,
		    <&clks IMX6UL_CLK_ENET_REF>,
		    <&clks IMX6UL_CLK_ENET_REF>;
	clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
	stop-mode = <&gpr 0x10 3>;
	fsl,num-tx-queues=<1>;
	fsl,num-rx-queues=<1>;
	fsl,magic-packet;
	fsl,wakeup_irq = <0>;
	status = "disabled";
};

fec2: ethernet@020b4000 {
	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	reg = <0x020b4000 0x4000>;
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ENET>,
		    <&clks IMX6UL_CLK_ENET_AHB>,
		    <&clks IMX6UL_CLK_ENET_PTP>,
		    <&clks IMX6UL_CLK_ENET2_REF_125M>,
		    <&clks IMX6UL_CLK_ENET2_REF_125M>;
	clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
	stop-mode = <&gpr 0x10 4>;
	fsl,num-tx-queues=<1>;
	fsl,num-rx-queues=<1>;
	fsl,magic-packet;
	fsl,wakeup_irq = <0>;
	status = "disabled";
};

IOMUX configuration

ConnectCore 6UL SBC Pro device tree
pinctrl_enet1: enet1grp {
	fsl,pins = <
		MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
		MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
		MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
		MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
		MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
		MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
		MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
		MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
	>;
};

pinctrl_enet2: enet2grp {
	fsl,pins = <
		MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
		MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
		MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
		MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
		MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
		MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
		MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
		MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
	>;
};

/*
 * The same pins GPIO1_IO6 and GPIO_IO7 are shared as the MII
 * bus of ENET1 and ENET2. If both interfaces are enabled, the
 * IOMUX of ENET2 will apply.
 * If only one interface is enabled, the IOMUX of the enabled
 * interface will apply.
 */
pinctrl_enet1_mdio: mdioenet1grp {
	fsl,pins = <
		MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
		MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
	>;
};

pinctrl_enet2_mdio: mdioenet2grp {
	fsl,pins = <
		MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
		MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
	>;
};

pinctrl_enet1_gpio: enet1gpiogrp {
	fsl,pins = <
		/* ENET1_INT */
		MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x1b0b0
	>;
};

pinctrl_enet2_gpio: enet2gpiogrp {
	fsl,pins = <
		/* PHY reset */
		MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0
		/* ENET2_INT */
		MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x1b0b0
	>;
};

Ethernet enabling and PHY parameters

ConnectCore 6UL SBC Pro device tree
&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-reset-gpios = <&mca_gpio 7 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <26>;
	digi,phy-reset-in-suspend;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>,
		    <&pinctrl_enet2_mdio>,
		    <&pinctrl_enet2_gpio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <26>;
	digi,phy-reset-in-suspend;
	status = "okay";

	/*
	 * The MDIO bus is shared between ENET1 and ENET2. If you only want
	 * to enable ENET1, this node must be moved to fec1 node, and the
	 * pinctrl-0 of fec1 must contain the IOMUX for the MDIO bus on ENET1
	 * (pintrl_enet1_mdio).
	 */
	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <1>;
		};
	};
};

Use only Ethernet port 1

The two Ethernet ports share the MDIO bus. When both ports are enabled, the definition of the MDIO bus on the device tree needs to be declared inside the second Ethernet port (fec2). This is the default configuration on the ConnectCore 6UL SBC Pro device tree.

To use only Ethernet port 1 (fec1), do the following changes on the device tree:

  1. Move the MDIO bus declaration from fec2 to fec1 node.

  2. Add pinctrl_enet1_mdio to the pinctrl list of fec1.

  3. Disable fec2 on your final dts file.

See here a patch that does such changes:

diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbc-wb.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbc-wb.dts
index de3911f1a402..17d73d2084e2 100644
--- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbc-wb.dts
+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbc-wb.dts
@@ -66,7 +66,7 @@

 /* ENET2 */
 &fec2 {
-       status = "okay";
+       status = "disabled";
 };

 /* CAN1 (multiplexed with UART3 RTS/CTS) */
diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dts
index 26c09cbefc7d..86d056d44a2b 100644
--- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dts
+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dts
@@ -66,7 +66,7 @@

 /* ENET2 */
 &fec2 {
-       status = "okay";
+       status = "disabled";
 };

 /* CAN1 (multiplexed with UART3 RTS/CTS) */
diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dtsi
index b1d53cf832e3..4d051d52e64d 100644
--- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dtsi
+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbc.dtsi
@@ -103,26 +103,15 @@

 &fec1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
+       pinctrl-0 = <&pinctrl_enet1>,
+                   <&pinctrl_enet1_mdio>,
+                   <&pinctrl_enet1_gpio>;
        phy-mode = "rmii";
        phy-handle = <&ethphy0>;
        phy-reset-gpios = <&mca_gpio 7 GPIO_ACTIVE_LOW>;
        phy-reset-duration = <26>;
        digi,phy-reset-in-suspend;
        status = "disabled";
-};
-
-&fec2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet2>,
-                   <&pinctrl_enet2_mdio>,
-                   <&pinctrl_enet2_gpio>;
-       phy-mode = "rmii";
-       phy-handle = <&ethphy1>;
-       phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
-       phy-reset-duration = <26>;
-       digi,phy-reset-in-suspend;
-       status = "disabled";

        /*
         * The MDIO bus is shared between ENET1 and ENET2. If you only want
@@ -148,6 +137,19 @@
        };
 };

+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2>,
+                   <&pinctrl_enet2_mdio>,
+                   <&pinctrl_enet2_gpio>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy1>;
+       phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <26>;
+       digi,phy-reset-in-suspend;
+       status = "disabled";
+};
+
 /* CAN1 */
 &can1 {
        pinctrl-names = "default";

MAC addresses

The MAC addresses of the {cpu-family} Ethernet interfaces are programmed in the U-Boot environment (variables ethaddr and eth1addr) on the ConnectCore 6UL NAND. The MAC address of the first Ethernet interface is also printed on the module label. U-Boot writes the MAC addresses in the ethaddr and ethaddr1 environment variables into their respective device tree fec nodes under the local-mac-address property. For more information, see Environment variables.

Ethernet user space usage

In the Linux system, the Ethernet interfaces are known as ethX where X is a number, starting at 0, that indicates the interface index. The Ethernet (FEC) driver exposes device data through the sysfs at /sys/class/net/ethX. You can use NetworkManager to configure Ethernet settings such as IP and netmask.