The NXP i.MX93 CPU has eight low-power SPI (LPSPI) buses.

On the ConnectCore 93 system-on-module:

  • All eight LPSPI ports are available (multiplexed with other functionality) either on the castellated or LGA pads.

On the ConnectCore 93 Development Kit:

  • One SPI bus is available on the mikroBUS™ connector.

Kernel configuration

You can manage the SPI driver support through the kernel configuration option:

  • Freescale i.MX LPSPI controllers in master mode (CONFIG_SPI_FSL_LPSPI)

  • Freescale QSPI controller (CONFIG_SPI_FSL_QUADSPI)

This options are enabled as built-in on the default ConnectCore 93 kernel configuration file.

Kernel driver

File Description


Freescale i.MX LPSPI controllers in master mode


Freescale QSPI controller

Device tree bindings and customization

The i.MX93 SPI interface device tree binding is documented at Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml.

The common i.MX93 CPU device tree defines all the SPI ports. The platform device tree must:

  • Enable the required SPI port, by setting the status property to "okay".

  • Choose the chip selects using property cs-gpios and their number using property fsl,spi-num-chipselects.

  • Configure the IOMUX of the pads that will work as SPI port.

  • Add the SPI slave devices as children of the SPI bus node.

SPI user space usage

The SPI bus cannot be accessed directly from user space. Instead, it is accessed via the SPI client drivers.

Sample application

An example application called apix-spi-example is included in the dey-examples-digiapix recipe (part of dey-examples package) of the meta-digi layer. This application is an example of how to write data to an external EEPROM (24FC1026) and read it back using Digi APIx library on the ConnectCore 93 platform.

Go to GitHub to see the application instructions and source code.

See SPI API for more information about the SPI APIx.