Video

dsi: dsi@4ae10000 {
	compatible = "fsl,imx93-mipi-dsi";
	reg = <0x4ae10000 0x4000>;
	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>,
		<&clk IMX93_CLK_MIPI_DSI_GATE>,
		<&clk IMX93_CLK_MEDIA_DISP_PIX>;
	clock-names = "byte", "pclk", "pixel";
	assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>,
			<&clk IMX93_CLK_MEDIA_APB>;
	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>,
			<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
	assigned-clock-rates = <20000000>, <133333333>;
	phys = <&dphy>;
	phy-names = "dphy";
	power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
	status = "disabled";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			dsi_to_lcdif: endpoint {
				remote-endpoint = <&lcdif_to_dsi>;
			};
		};
	};
};

lcdif: lcd-controller@4ae30000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx93-lcdif";
	reg = <0x4ae30000 0x10000>;
	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	fsl,gpr = <&media_blk_ctrl>;
	clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>,
		<&clk IMX93_CLK_MEDIA_AXI>,
		<&clk IMX93_CLK_LCDIF_GATE>;
	clock-names = "pix", "disp-axi", "disp-apb";
	assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>,
			<&clk IMX93_CLK_MEDIA_DISP_PIX>,
			<&clk IMX93_CLK_MEDIA_AXI>,
			<&clk IMX93_CLK_MEDIA_APB>;
	assigned-clock-parents = <&clk IMX93_CLK_24M>,
				<&clk IMX93_CLK_VIDEO_PLL>,
				<&clk IMX93_CLK_SYS_PLL_PFD1>,
				<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
	power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>;
	status = "disabled";

	lcdif_disp: port@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>;

		lcdif_to_dsi: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&dsi_to_lcdif>;
		};

		lcdif_to_ldb: endpoint@1 {
			reg = <1>;
			remote-endpoint = <&ldb_ch0>;
		};

		lcdif_to_dpi: endpoint@2 {
			reg = <2>;
			remote-endpoint = <&dpi_to_lcdif>;
		};
	};
};